In the fabrication of semiconductor chips, an important step is selectively etching and/or adding metal to selected portions of the completed chip in order to debug problem areas. Typically, this involves using a focused ion beam (FIB) system in the desired areas in order to remove and/or add selected connector portions. The desired areas are usually identified by the FIB system using topological features for imaging contrast and navigation to the regions of interest. The FIB systems can then add or remove features depending on the gas applied.
In some devices, however, the entire chip is covered by one or more planarization layers, thereby hiding the topographical features which are used for aligning the focused ion beam. In some cases, the only features resolvable by the FIB system are the bonding pads. However, since the accuracy desired for FIB is generally in the range 0.1 to 0.2 microns, the pads cannot be used for alignment.
It is desirable, therefore, to provide a process permitting navigation of a focused ion beam on an otherwise planar Integrated Circuit (IC) chip.